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R.Belmont: the ESQ-1 driver needs a 2681 Duart: the 68681 duart core will handle this just fine, just set the interrupts up to ignore the 'vector' parameter. Otherwise the 68681 and 2681 duarts are practically completely identical (the only differences are detailed in the appendix A of this datasheet: http://www.cs.indiana.edu/csg/hardware/c335_tools/MC68681UM.pdf ; in short: the 68681 duart is 68k aware, hence has an /INTACK pin and an IVR register, while the 2681 is general purpose and has an IP6 pin instead, and the *reserved* reg in place of the IVR reg doesn't do anything except store a byte of data. Also the 2681 has a RESET pin and 68681 has /RESET pin, and the secondary purposes of the IPx pins are shuffled around a bit)

Be warned that the 68681 core is still missing a number of features: there is no way (that I've found) to push an interrupt state update if it has delta interrupts set up for the ip0/ip1/ip2/ip3 input pins; the hardware rts/cts control for channels A/B based on pins ip0/ip1 and op0/op1 (controlled by MR2A/B bits 4 and 5) is also not implemented yet, but I plan to add this soon.
Also the counter/timer modes which depend on the input pins are not implemented, and implementing them would seem to require a full state machine emulation of the core, which would require a ground-up rewrite. Also emulating actually reading the counter registers will be a little tricky, though timed interrupts do work right now using timers for the full count duration.

LN