The I-RAM and BW-RAM are visible to both chips. To aid in letting bsnes run out-of-order, and because only the SA-1 can make use of the bitmap-RAM projection mode, I have access interfaces for both chips. There's also some special stuff to handle character-conversion DMAs.
cc1 refers to character-conversion mode 1, while sa1 is usually referring to bog-standard SA-1 opcode memory accesses. I'll have to look at the code sometime to explain it better why I have both.
And not only the CPU, you need to support part of the SA-1 MMIO interface to let the main CPU start the SA-1 at a specified point.
