Originally Posted By Lord Nightmare
And hopefully any future changes to fix the one case so far will not require gutting and redoing the entire s-cpu core...

The worst possible thing that could happen is having my hold times for reads and writes disproven somehow. That would require adjusting every last timing value (when does Hblank start/stop, when does DMA transfer begin, etc) by +/-2 or whatever.

Nothing really major.

I also don't have the first idea how to verify it. All I know is that reading from $2137 latches the counters at N, and writing to $4201 latches them at N+4 master clock cycles.

Since they are FastROM, I extrapolate that to means writes "occur" at cycle_start+cycle_length, and reads "occur" at cycle_start+cycle_length-4.

TRAC concurred based off timing information in the official 65816 doc, but that doesn't mean it doesn't vary depending upon which chip / register you are accessing.

I don't have any way to verify that, need a hardware guru to go at it with an oscilliscope or something.