Yeah, Matty has successfully ended my enthusiasm for attempting anything with PPC NT - our PowerPC core doesn't support LE, and that description of it is frankly terrifying.
Oh no, fucking horrifying, having to make a variant of the PowerPC core that has overridden load/store opcodes and nothing else! The horror, the horror! :P
It's a bit more complicated than that - the chip always starts in BE mode on reset, and you can change it with a privileged SFR. You can also set different endian modes for interrupt code and user code, and the chip will conveniently switch on entering and leaving interrupt handlers. This lets you run a BE app on an LE board as long as it doesn't try to do I/O and vice versa.
So the main PPC core should really be checking the SFRs that control endian mode on all load and store instructions when computing the effective address, and this step should be skipped for PPC variants that don't support LE mode (e.g. some embedded ones in the 4xx series).
As to how you emulate the bus being wired backwards on a LE board, I have no clue.
